1. Field of the Invention
The present invention relates to integrated circuits, and more particularly, to using TAP controllers.
2. Background
Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and storage devices (for example, tape drives, disk drives etc.) (referred to herein as “storage device”)
In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
The storage device is coupled to the host system via a storage device controller that handles complex details of interfacing the storage device(s) to the host system. Communications between the host system and the controller is usually provided using one of a variety of standard input/output (“I/O”) bus interfaces.
Storage controllers are coupled using various standards, for example, the fibre channel standard incorporated herein by reference in its entirety.
As bandwidth increases, host systems and storage devices must transfer data efficiently. Because of high demand, it is desirable that the internal register files of integrated circuits (also referred to as “chips”) used in (or as) storage controllers be accessed real-time without disrupting normal chip operation for de-bugging or any other purpose.
A standard, IEEE 11491.1 and 11491A was developed (referred to as the JTAG standard) for testing of integrated circuits after assembly onto a printed circuit board, incorporated herein by reference in its entirety. The JTAG standard provides for testing numerous integrated circuits on a board as well as the interconnection of those circuits to the printed conductors of the board. Testing is performed using pins associated with a test access port (“TAP”).
TAP controllers are used to access chip information at a tap controller clock (tclk). In traditional systems, all chip operations stop when a chip is debugged using the JTAG standard. This is commercially undesirable because engineers may want to access the internal registers of a chip while it is operational.
Therefore, there is a need for a method and system that allows dynamic access to a chip via a TAP port during normal chip operation.